基于动态亚阈值的延迟型PUF电路设计

张笑天; 汪鹏君; 张跃军; 张会红

doi:10.14135/j.cnki.1006-3080.20210203001

基于动态亚阈值的延迟型PUF电路设计

doi: 10.14135/j.cnki.1006-3080.20210203001

张笑天^1,,
汪鹏君^{1, 2, ,},
张跃军¹,
张会红¹

1.
宁波大学电路与系统研究所，浙江宁波 315211
2.
温州大学电气与电子工程学院，浙江温州 325035

基金项目: 国家自然科学基金(61874078，61871244)；国家重点研发计划项目(2018YFB2202100)

详细信息

作者简介:
张笑天(1994-)，男，硕士生，主要从事安全芯片理论与设计。E-mail：1811082172@nbu.edu.cn

通讯作者:
汪鹏君，E-mail：wangpengjun@wzu.edu.cn

中图分类号: TP79
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- 被引次数: 0
出版历程
- 收稿日期: 2021-02-03
- 网络出版日期: 2021-06-22

A Delayed PUF Based on Dynamic Subthreshold Logic

1.
Institute of Circuits and System, Ningbo University, Ningbo 315211, Zhejiang, China
2.
College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou 325035, Zhejiang, China

摘要

摘要: 物理不可克隆函数(Physical Unclonable Function, PUF)电路能有效抵御侵入式物理攻击，但是随着芯片集成度以及物联网技术的不断提高，模型攻击、有限能耗预算等不仅严重威胁PUF电路的安全性，而且限制PUF电路的能效。通过对PUF电路以及亚阈值逻辑的研究，提出了一种基于动态亚阈值的延迟型PUF电路设计方案。该方案首先利用亚阈值压控电路构成输出函数非线性部分；然后利用电荷分享效应改变输出电压初始值，形成随激励信号变化的非线性输出函数；最后通过动态亚阈值判决器输出PUF响应。电路采用TSMC 65nm CMOS工艺设计，并通过HSPICE验证，能耗为0.23 pJ/bit，与同类电路相比降低了23.3%，并具有良好的抗模型攻击特性。
- 物理不可克隆函数 /
- 动态亚阈值延迟 /
- 模型攻击 /
- 低功耗
Abstract: Physical Unclonable Function (PUF) circuits show good resistance to intrusive physical attacks. However, with the continuous improvement of chip integration and IoT (Internet of Things) technology, model attacks and limited energy budgets not only seriously threaten the security of PUF circuits, but also limit the energy efficiency of PUF circuits. In this paper, a delayed PUF structure based on dynamic subthreshold logic is proposed. First, the structure utilizes a sub-threshold voltage control circuit to form the nonlinear part of the output function. Then the initial value of the output voltage is modified by charge sharing effect, hence the nonlinear output function varies with the challenge input. Finally, the PUF response is outputted by a dynamic subthreshold arbiter. The proposed PUF is designed in TSMC 65 nm CMOS Technology and verified by HSPICE tool. Experimental results show that it can effectively resist model attacks and has an energy consumption of 0.23pJ/bit which is 23.3% lower than similar circuits.
- physical unclonable function /
- dynamic subthreshold delay /
- model attack /
- low power

HTML全文

图 1 仲裁器PUF结构

Figure 1. Architecture of the arbiter PUF

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图 2 静态与非门和动态与非门

Figure 2. Static and dynamic NAND gate

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图 3 混合延迟单元电路

Figure 3. Hybrid delayed cell circuit

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图 4 动态亚阈值判决器

Figure 4. Dynamic subthreshold arbiter

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图 5 1位DSD PUF单元框图

Figure 5. 1-bit DSD PUF cell block diagram

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图 6 N位DSD PUF电路框图

Figure 6. N-bit DSD PUF block diagram

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图 7 密钥提取时序图

Figure 7. Timing diagram of key extraction

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图 8 能耗分布

Figure 8. Energy consumption distribution

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图 9 2 000次蒙特卡洛仿真结果

Figure 9. 2 000 times Monte Carlo simulation results

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图 10 DSD PUF汉明距离分布

Figure 10. Hamming distance distribution of DSD PUF

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图 11 ANN算法预测错误率

Figure 11. Prediction error rate by ANN algorithm

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图 12 极端温度下的蒙特卡洛仿真情况

Figure 12. Monte Carlo simulation in worst temperature condition

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图 13 不同温度、电压下的误码率

Figure 13. BER against temperature and voltage variations

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表 1 性能比较结果

Table 1. Comparison of the qualities of PUFs

Circuit	Process/nm	Voltage/V	Energy/(pJ·bit⁻¹)	BER/%	Entropy
literature[6]	130	1.08~1.32	11	0.4	0.999 993 575
literature[11]	65	0.6~1.2	0.5	0.44	0.995 398 306
literature[12]	130	0.9~1.2	1.6	2.06	0.994 512 917
literature[13]	65	0.8~1.0	0.3	10.9	0.999 999 879
This work	65	0.3~0.5	0.23	2.19	0.999 999 279

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参考文献(13)

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