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  • ISSN 1006-3080
  • CN 31-1691/TQ

基于动态亚阈值的延迟型PUF电路设计

张笑天 汪鹏君 张跃军 张会红

张笑天, 汪鹏君, 张跃军, 张会红. 基于动态亚阈值的延迟型PUF电路设计[J]. 华东理工大学学报(自然科学版). doi: 10.14135/j.cnki.1006-3080.20210203001
引用本文: 张笑天, 汪鹏君, 张跃军, 张会红. 基于动态亚阈值的延迟型PUF电路设计[J]. 华东理工大学学报(自然科学版). doi: 10.14135/j.cnki.1006-3080.20210203001
ZHANG Xiaotian, WANG Pengjun, ZHANG Yuejun, ZHANG Huihong. A Delayed PUF Based on Dynamic Subthreshold Logic[J]. Journal of East China University of Science and Technology. doi: 10.14135/j.cnki.1006-3080.20210203001
Citation: ZHANG Xiaotian, WANG Pengjun, ZHANG Yuejun, ZHANG Huihong. A Delayed PUF Based on Dynamic Subthreshold Logic[J]. Journal of East China University of Science and Technology. doi: 10.14135/j.cnki.1006-3080.20210203001

基于动态亚阈值的延迟型PUF电路设计

doi: 10.14135/j.cnki.1006-3080.20210203001
基金项目: 国家自然科学基金(61874078,61871244);国家重点研发计划项目(2018YFB2202100)
详细信息
    作者简介:

    张笑天(1994-),男,硕士生,主要从事安全芯片理论与设计。E-mail:1811082172@nbu.edu.cn

    通讯作者:

    汪鹏君,E-mail:wangpengjun@wzu.edu.cn

  • 中图分类号: TP79

A Delayed PUF Based on Dynamic Subthreshold Logic

  • 摘要: 物理不可克隆函数(Physical Unclonable Function, PUF)电路能有效抵御侵入式物理攻击,但是随着芯片集成度以及物联网技术的不断提高,模型攻击、有限能耗预算等不仅严重威胁PUF电路的安全性,而且限制PUF电路的能效。通过对PUF电路以及亚阈值逻辑的研究,提出了一种基于动态亚阈值的延迟型PUF电路设计方案。该方案首先利用亚阈值压控电路构成输出函数非线性部分;然后利用电荷分享效应改变输出电压初始值,形成随激励信号变化的非线性输出函数;最后通过动态亚阈值判决器输出PUF响应。电路采用TSMC 65nm CMOS工艺设计,并通过HSPICE验证,能耗为0.23 pJ/bit,与同类电路相比降低了23.3%,并具有良好的抗模型攻击特性。

     

  • 图  1  仲裁器PUF结构

    Figure  1.  Architecture of the arbiter PUF

    图  2  静态与非门和动态与非门

    Figure  2.  Static and dynamic NAND gate

    图  3  混合延迟单元电路

    Figure  3.  Hybrid delayed cell circuit

    图  4  动态亚阈值判决器

    Figure  4.  Dynamic subthreshold arbiter

    图  5  1位DSD PUF单元框图

    Figure  5.  1-bit DSD PUF cell block diagram

    图  6  N位DSD PUF电路框图

    Figure  6.  N-bit DSD PUF block diagram

    图  7  密钥提取时序图

    Figure  7.  Timing diagram of key extraction

    图  8  能耗分布

    Figure  8.  Energy consumption distribution

    图  9  2 000次蒙特卡洛仿真结果

    Figure  9.  2 000 times Monte Carlo simulation results

    图  10  DSD PUF汉明距离分布

    Figure  10.  Hamming distance distribution of DSD PUF

    图  11  ANN算法预测错误率

    Figure  11.  Prediction error rate by ANN algorithm

    图  12  极端温度下的蒙特卡洛仿真情况

    Figure  12.  Monte Carlo simulation in worst temperature condition

    图  13  不同温度、电压下的误码率

    Figure  13.  BER against temperature and voltage variations

    表  1  性能比较结果

    Table  1.   Comparison of the qualities of PUFs

    CircuitProcess/nmVoltage/VEnergy/(pJ·bit−1)BER/%Entropy
    literature[6]1301.08~1.32110.40.999 993 575
    literature[11]650.6~1.20.50.440.995 398 306
    literature[12]1300.9~1.21.62.060.994 512 917
    literature[13]650.8~1.00.310.90.999 999 879
    This work650.3~0.50.232.190.999 999 279
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  • [1] CAO Y, ZHANG L, CHANG C, et al. A low-power hybrid RO PUF with improved thermal stability for lightweight applications[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34(7): 1143-1147. doi: 10.1109/TCAD.2015.2424955
    [2] ZHAO X, GAN P, ZHAO Q, et al. A 124 fJ/bit cascade current mirror array based PUF with 1.50% native unstable bit ratio[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(9): 3494-3503. doi: 10.1109/TCSI.2019.2927758
    [3] WANG S, CHEN Y, LI K. Adversarial attack against modeling attack on PUFs[C]// 2019 56th ACM/IEEE Design Automation Conference (DAC). USA: IEEE, 2019: 1-6.
    [4] SHI J, LU Y, ZHANG J. Approximation attacks on strong PUFs[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39(10): 2138-2151. doi: 10.1109/TCAD.2019.2962115
    [5] TAO S, DUBROVA E. Ultra-energy-efficient temperature-stable physical unclonable function in 65 nm CMOS[J]. Electronics Letters, 2016, 52(10): 805-806. doi: 10.1049/el.2016.0292
    [6] ZHUANG H, XI X, SUN N, et al. A strong subthreshold current array PUF resilient to machine learning attacks[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(1): 135-144. doi: 10.1109/TCSI.2019.2945247
    [7] XI X, ZHUANG H, SUN N, et al. Strong subthreshold current array PUF with 265 challenge-response pairs resilient to machine learning attacks in 130nm CMOS[C]// Symposium on VLSI Circuits. Japan: IEEE, 2017: 268-269.
    [8] LIN L, SRIVATHSA S, KRISHNAPPA D, et al. Design and validation of arbiter-based PUFs for sub-45-nm low-power security applications[J]. IEEE Transactions on Information Forensics and Security, 2012, 7(4): 1394-1403. doi: 10.1109/TIFS.2012.2195174
    [9] ZALIVAKA S, IVANIUK A, CHANG C. Reliable and modeling attack resistant authentication of arbiter PUF in FPGA implementation with trinary quadruple response[J]. IEEE Transactions on Information Forensics and Security, 2019, 14(4): 1109-1123. doi: 10.1109/TIFS.2018.2870835
    [10] SANTIKELLUR P, CHAKRABORTY R. A computationally efficient tensor regression network based modeling attack on XOR arbiter PUF and its variants[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020: 1-1.
    [11] LI J, SEOK M. Ultra-compact and robust physically unclonable function based on voltage compensated proportional-to-absolute- temperature voltage generators[J]. IEEE Journal of Solid-State Circuits, 2016, 51(9): 2192-2202. doi: 10.1109/JSSC.2016.2586498
    [12] SU Y, HOLLEMAN J, OTIS B. A digital 1.6 pJ/bit chip identification circuit using process variations[J]. IEEE Journal of Solid-State Circuits, 2008, 43(1): 69-77. doi: 10.1109/JSSC.2007.910961
    [13] VENKATESH A, VENKATASUBRAMANIYAN A, XI X, et al. 0.3 pJ/bit machine learning resistant strong PUF using subthreshold voltage divider array[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2020, 57(8): 1394-1398.
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出版历程
  • 收稿日期:  2021-02-03
  • 网络出版日期:  2021-06-22

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