基于异构FPGA的目标检测硬件加速器架构设计

夏琪迪; 颜秉勇; 周家乐; 王慧锋

doi:10.14135/j.cnki.1006-3080.20201027003

基于异构FPGA的目标检测硬件加速器架构设计

doi: 10.14135/j.cnki.1006-3080.20201027003

华东理工大学信息科学与工程学院，上海 200237

基金项目: 国家重点研发计划（2018YFC1803306）；青年科学基金（61906068）

详细信息

作者简介:
夏琪迪（1998—），男，安徽亳州人，硕士生，主要研究方向为FPGA、嵌入式系统。E-mail：2389240877@qq.com

通讯作者:
颜秉勇，E-mail：byyan@ecust.edu.cn

中图分类号: TP183; TP368.2
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- 文章访问数: 857
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- 被引次数: 0
出版历程
- 收稿日期: 2020-10-27
- 网络出版日期: 2021-01-19
- 刊出日期: 2021-12-30

Architecture Design of Target Detection Hardware Accelerator Based on Heterogeneous FPGA

School of Information Science and Engineering, East China University of Science and Technology, Shanghai 200237, China

摘要

摘要: 采用粗细粒度优化、参数定点化与重排序等多种硬件加速方法，基于FPGA+SOC异构平台提出了一种低功耗目标检测加速器架构。针对现有研究的设计局限性，在Zynq 7000 系列FPGA上对YOLOv2算法进行新型多维度硬件加速，并对加速器性能和资源耗费进行深入分析建模，验证架构的合理性；为充分利用片上硬件资源，对各个模块进行特定优化设计，针对被忽视的底层繁琐数据访问，改进加速器数据访存机制，有效减少了系统传输时延。实验结果表明，该架构在PYNQ-Z2平台上获得了26.98 GOPs的性能，比现有的基于FPGA的目标检测平台提高了约38.71%，功耗仅为2.96 W，对目标检测算法的实际应用具有深远意义。
- 现场可编辑门阵列 /
- 目标检测 /
- 硬件加速 /
- 高层次综合
Abstract: In recent years, with the continuous breakthrough in the field of algorithms, the current target detection algorithms have higher and higher computational complexity. In the forward inference stage, many practical applications often face low latency and strict power consumption restrictions. How to realize a low-power, low-cost, and high-performance target detection platform has gradually attracted more attention. As a high-performance, reconfigurable and low-cost embedded platform, Field Programmable Gate Array (FPGA) is becoming the key technology of algorithm application. In view of the above requirements, this paper proposes a low-power target detection accelerator architecture based on FPGA+SOC (System On Chip) heterogeneous platform by adopting various hardware acceleration methods such as coarse and fine granularity optimization, parameter fixed-point and reordering. Aiming at the design limitation of existing researches on Zynq 7000 series FPGA, this paper proposes a new multi-dimensional hardware acceleration of YOLOv2 (You Only Look Once) algorithm, and deeply analyzes and models the accelerator performance and resource consumption to verify the rationality of the architecture. In order to make full use of the on-chip hardware resources to optimize the design of each module, the accelerator data access mechanism is improved to effectively reduce the transmission delay of the system and improve the actual utilization rate of bus bandwidth. The fixed-point processing of floating-point numbers can reduce the processing load of FPGA and further accelerate the processing speed. It is shown via experiments that the architecture achieves 26.98 GOPs performance on PYNQ-Z2 platform, which is about 38.71% higher than the existing FPGA-based target detection platform, and the power consumption is only 2.96 W. Moreover, it has far-reaching significance for the application of target detection algorithm.
- field programmable gate array /
- target detection /
- hardware acceleration /
- high-level integration

HTML全文

图 1 YOLOv2网络结构

Figure 1. YOLOv2 network structure

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图 2 加速器数据流框架

Figure 2. Accelerator data flow framework

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图 3 粗粒度优化示意图

Figure 3. Schematic diagram of coarse-grained optimization

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图 4 优化前后FPGA中的乘加操作对比

Figure 4. Comparison of multiplication and addition operations in FPGA before and after optimization

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图 5 32位浮点数和16位定点数表示对比

Figure 5. Comparison between 32-bit floating-point numbers and 16-bit fixed-point numbers

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图 6 卷积模块展开示意图

Figure 6. Schematic diagram of convolution module expansion

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图 7 池化模块示意图

Figure 7. Schematic diagram of pooling module

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图 8 重排序示意图

Figure 8. Schematic diagram of reordering

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图 9 系统硬件加速器架构

Figure 9. System hardware accelerator architecture

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图 10 YOLOv2网络硬件加速系统

Figure 10. YOLOv2 network hardware acceleration system

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图 11 实验环境与检测结果

Figure 11. Experimental environment and test results

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表 1 不同数据精度消耗资源对比

Table 1. Comparison of resource consumption with different data accuracy

Consume resources (Data precision)	DSP	LUT
Adders（Float-32）	2	214
Multiplier（Float-32）	3	135
Adders（Fixed-16）	−	47
Multiplier（Fixed-16）	1	101

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表 2 加速器资源消耗

Table 2. Accelerator resource consumption

Resoures	Used	Available	Utilization/%
LUTs	35 977	53 200	67.62
FF	32 049	106 400	30.12
BRAM_18K	178	280	63.57
DSP48E	152	220	69.09

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表 3 与其他FPGA加速器设计的比较

Table 3. Comparison with other FPGA accelerator designs

Accelerator	CNN Model	Platform	Frequency/ MHz	BRAM	DSP	Power/W	Performance /GOPs
Ref[22]	YOLOv1	ZC706	200	N/A	800	2.17	18.82
Ref[13]	LW YOLOv2	Zynq Ultra	300	1706	377	4.50	N/A
Ref[23]	YOLOv2 Tiny	Cyclone V	117	N/A	122	N/A	19.45
This work	YOLOv2	PYNQ-Z2	150	178	152	2.96	26.98

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