Design of Low-Swing Clock Ternary Low Power Double Edge-Triggered Flip-Flop

By analyzing the existing multiple-value flip-flop, this paper proposes a novel design scheme of feedbackkeeper lowswing clock ternary low-power double edge triggered flip-flop (FK-LSCTLPDFF). The proposed flip-flop avoids the incorrect shift caused by the input pulse by using the feedbackdeeper. In a TDETFF , both the rising and falling edges of the clock signal are used to transfer data from input to output so as to restrain the redundancy of the clock signal. In this way, for a given throughput, the clock frequency can be halved with respect to a system by using ternary single-edge triggered flip-flop (TSETFF), with a reduction of power dissipation. Finally, the PSPICE simulation results indicate that the novel scheme has correct logic function and the character of clearly low power.