RTL Symbolic Simulation System

KUANG Xiang, SONG Guo-xin~*. RTL Symbolic Simulation System[J]. Journal of East China University of Science and Technology, 2004, (6): 673-676.

Citation:

KUANG Xiang, SONG Guo-xin~*. RTL Symbolic Simulation System[J]. Journal of East China University of Science and Technology, 2004, (6): 673-676.

Citation:

KUANG Xiang, SONG Guo-xin~*. RTL Symbolic Simulation System[J]. Journal of East China University of Science and Technology, 2004, (6): 673-676.

Abstract

We present a set of rules, which can translate Verilog HDL specifications into executable symbolic codes, and a processQueue mechanism. We propose a method of implementing a symbolic simulation system which uses symbolic simulation and BDD. Our system can effectively simulate RTL Verilog, and support if-then-else structure with time delay.

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