A Novel Low Power Scheduling Algorithm for Functional Unit Power Gating in High-Level Synthesis

Power gating technology is a low-energy circuit design widely used recently. It can optimize the circuit energy consumption by reasonably switching the power supply of the module circuit. In this paper, an algorithm integrating both the scheduling and binding processes is developed for the fine-grained functional unit (FU) power-gating technique so as to achieve the maximum leakage energy reduction. Firstly, the break-even points of FUs are analyzed, and the leakage energy reduction problem is formulated as an idle interval partition problem. Secondly, the penalty duration of idle interval length under different scheduling result is analyzed. Besides, the operation is scheduled to the clock cycle with minimum penalty time. Finally, the experimental results show that the proposed algorithms can significantly reduce the energy consumption of the circuit without increasing the circuit area and working delay, and provides better design solution for spaceborne platform equipment.