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    GONG Dao-hui, WANG Peng-jun, KANG Yao-peng, ZHANG Hui-hong. Design of High-Speed and Low-Power Ternary Sense Amplifier Based on CNFET[J]. Journal of East China University of Science and Technology, 2017, (2): 248-253. DOI: 10.14135/j.cnki.1006-3080.2017.02.015
    Citation: GONG Dao-hui, WANG Peng-jun, KANG Yao-peng, ZHANG Hui-hong. Design of High-Speed and Low-Power Ternary Sense Amplifier Based on CNFET[J]. Journal of East China University of Science and Technology, 2017, (2): 248-253. DOI: 10.14135/j.cnki.1006-3080.2017.02.015

    Design of High-Speed and Low-Power Ternary Sense Amplifier Based on CNFET

    • By researching the structure of Carbon Nanotube Field Effect Transistor (CNFET) and the principle of sense amplifier,a scheme of high-speed and low-power ternary sense amplifier circuit is proposed.In this scheme,the circuit structure of a ternary inverter is analyzed.And then,we use cross-coupled inverters method to implant a ternary latch.To improve the speed of differential signal amplification,the input and output signal separation technique is selected.And also,the working states are controlled by enable signal to reduce the power consumption of ternary sense amplifier circuit.Under Stanford University 32 nm CNFET standard model,HSPICE simulation results show that the designed circuit has correct logic functionality.The chip yield of the circuit is up to 96.48% with strong stability.Comparing with conventional binary CMOS sense amplifier,the proposed circuit increases the speed by 64%,and decreases the power consumption by 83.4%.
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