图共 11个 表共 3
    • 图  1  YOLOv2网络结构

      Figure 1.  YOLOv2 network structure

    • 图  2  加速器数据流框架

      Figure 2.  Accelerator data flow framework

    • 图  3  粗粒度优化示意图

      Figure 3.  Schematic diagram of coarse-grained optimization

    • 图  4  优化前后FPGA中的乘加操作对比

      Figure 4.  Comparison of multiplication and addition operations in FPGA before and after optimization

    • 图  5  32位浮点数和16位定点数表示对比

      Figure 5.  Comparison between 32-bit floating-point numbers and 16-bit fixed-point numbers

    • 图  6  卷积模块展开示意图

      Figure 6.  Schematic diagram of convolution module expansion

    • 图  7  池化模块示意图

      Figure 7.  Schematic diagram of pooling module

    • 图  8  重排序示意图

      Figure 8.  Schematic diagram of reordering

    • 图  9  系统硬件加速器架构

      Figure 9.  System hardware accelerator architecture

    • 图  10  YOLOv2网络硬件加速系统

      Figure 10.  YOLOv2 network hardware acceleration system

    • 图  11  实验环境与检测结果

      Figure 11.  Experimental environment and test results

    • Consume resources (Data precision)DSPLUT
      Adders(Float-32)2214
      Multiplier(Float-32)3135
      Adders(Fixed-16)-47
      Multiplier(Fixed-16)1101

      表 1  不同数据精度消耗资源对比

      Table 1.  Comparison of resource consumption with different data accuracy

    • ResouresUsedAvailableUtilization/%
      LUTs35 97753 20067.62
      FF32 049106 40030.12
      BRAM_18K17828063.57
      DSP48E15222069.09

      表 2  加速器资源消耗

      Table 2.  Accelerator resource consumption

    • AcceleratorCNN ModelPlatformFrequency/ MHzBRAMDSPPower/WPerformance /GOPs
      Ref[22]YOLOv1ZC706200N/A8002.1718.82
      Ref[13]LW YOLOv2Zynq Ultra30017063774.5N/A
      Ref[23]YOLOv2 TinyCyclone V117N/A122N/A19.45
      This WorkYOLOv2PYNQ-Z21501781522.9626.98

      表 3  与其他FPGA加速器设计的比较

      Table 3.  Comparison with other FPGA accelerator designs