嵌入式系统设计的一种协同仿真方法
A Co-simulation Method for Designing Embedded Systems
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摘要: 提出了一种基于C 平台的嵌入式系统设计的协同仿真方法。嵌入式系统的软件成分由C 实现,硬件成分由Verilog刻划。该方法的基本思路是将Verilog模块转化为C 程序,然后将软件成分与转化后的硬件成分连接,形成一个完整的仿真环境。Abstract: A co simulation method for hardware/software co design of embedded systems is proposed. An embedded system is composed of software parts in C++ and hardware parts in Verilog. The method aims to convert Verilog modules into C++ programs. Software portions are then integrated with the converted hardware parts and the result leads to a complete simulation environment.