一种高速全加器运算单元
A High Speed Unit of Full Adder
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摘要: 对集成芯片中一种常用单元电路——全加器,进行了结构和时延性能分析。通过运用布尔代数基本定律、定理,对全加器和函数进行全面处理,提取和函数最优化函数式。根据优化函数式,设计了高速全加器单元电路。这种电路与传统全加器单元电路相比,不仅结构简单,有利于集成,同时,由于电路传输延迟时间小,运算速度快。Abstract: Full adder is a base unit circuit of IC chip. This paper analyses the performances of architecture and delay time of a full adder, obtains sum's optimal NAND function with the laws and rules of boolean functions, and designs a high speed full adder circuit. At last, this paper compares the performances for two full adders.