Abstract: Owing to the dataintensive characteristics of the deblocking filter and the requirement of realtime video decoding, the hardware deblocking filtering accelerator has been recently receiving an increasing attention. Compared with the traditional hardware accelerators which support single standard for deblocking filtering, the proposed reconfigurable deblocking filter in this paper has the following advantages: Implement a deblocking architecture whose filtering algorithm can be reconfigured to support multiple video encoding standards; Adopt SIMD technology to attain the parallel computing of all filtering data, and the chip layout is easily made due to highly regular hardware structures; Design a 4stage assignable pipeline and reconfigure the deblocking filter for different video standards so as to enhance hardware utilization and system throughput. A multistandard accelerator deblocking filter supporting H264, AVS, VP8, and RealVideo standards is implemented with the clock frequency 200 MHz, which can be used for realtime multistandard HD video deblocking filtering.