Abstract: Analog to digital converter (ADC) is a key component in the integrated system-on-chip. By analyzing the successive approximation logic circuits and ternary logic, this paper proposes a designing scheme of ternary successive approximation register (SAR) ADC based on CNFET. Firstly, the ternary capacitor array backplane is supplied to different powers by control circuits. The values of analog is successively approximated so as to produce the corresponding two value signals. Secondly, the encoder transmits two value signals into ternary signal until the end of conversion. The simulation results on HSPICE show that the proposed algorithm has correct logic function, high speed, and low power consumption characteristics.