RTL级符号模拟系统
RTL Symbolic Simulation System
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摘要: 给出了一组从Verilog HDL到可符号执行代码的转换规则,并且提出了ProcessQueue机制。通过运用符号模拟的方法和二叉决策图技术,给出了一个RTL级的符号模拟系统的实现方法。本系统能够有效地对RTL级Verilog算法进行符号模拟,并且支持带有时间延迟的If结构的符号模拟。Abstract: We present a set of rules, which can translate Verilog HDL specifications into executable symbolic codes, and a processQueue mechanism. We propose a method of implementing a symbolic simulation system which uses symbolic simulation and BDD. Our system can effectively simulate RTL Verilog, and support if-then-else structure with time delay.