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    张笑天, 汪鹏君, 张跃军, 张会红. 基于动态亚阈值的延迟型PUF电路设计[J]. 华东理工大学学报(自然科学版), 2022, 48(2): 237-243. DOI: 10.14135/j.cnki.1006-3080.20210203001
    引用本文: 张笑天, 汪鹏君, 张跃军, 张会红. 基于动态亚阈值的延迟型PUF电路设计[J]. 华东理工大学学报(自然科学版), 2022, 48(2): 237-243. DOI: 10.14135/j.cnki.1006-3080.20210203001
    ZHANG Xiaotian, WANG Pengjun, ZHANG Yuejun, ZHANG Huihong. Design of Delayed PUF Circuit Based on Dynamic Subthreshold[J]. Journal of East China University of Science and Technology, 2022, 48(2): 237-243. DOI: 10.14135/j.cnki.1006-3080.20210203001
    Citation: ZHANG Xiaotian, WANG Pengjun, ZHANG Yuejun, ZHANG Huihong. Design of Delayed PUF Circuit Based on Dynamic Subthreshold[J]. Journal of East China University of Science and Technology, 2022, 48(2): 237-243. DOI: 10.14135/j.cnki.1006-3080.20210203001

    基于动态亚阈值的延迟型PUF电路设计

    Design of Delayed PUF Circuit Based on Dynamic Subthreshold

    • 摘要: 物理不可克隆函数(Physical Unclonable Function, PUF)电路能有效抵御侵入式物理攻击,但随着芯片集成度以及物联网技术的不断提高,模型攻击、有限能耗预算等不仅严重威胁PUF电路的安全性,而且限制PUF电路的能效。通过对PUF电路以及亚阈值逻辑的研究,提出了一种基于动态亚阈值的延迟型PUF电路设计方案。该方案首先利用亚阈值压控电路构成输出函数非线性部分;然后利用电荷分享效应改变输出电压初始值,形成随激励信号变化的非线性输出函数;最后通过动态亚阈值判决器输出PUF响应。电路采用TSMC 65nm CMOS工艺设计,并通过HSPICE验证,能耗为0.238 pJ/bit,与同类电路相比能耗降低了20.67%,并具有良好的抗模型攻击特性。

       

      Abstract: Physical unclonable function (PUF) circuits can effectively resist intrusive physical attacks. However, with the continuous improvement of chip integration and IoT (Internet of Things) technology, model attacks and limited energy budgets not only seriously threaten the security of PUF circuits, but also limit the energy efficiency of PUF circuits. By the study of PUF circuit and subthreshold logic, this paper proposes a design scheme of delay PUF circuit based on dynamic subthreshold. Firstly, a sub-threshold voltage control circuit is utilized to form the nonlinear part of the output function. And then, the initial value of the output voltage is modified by charge sharing effect to form a nonlinear output function that varies with the excitation signal. Finally, the PUF response is outputted by a dynamic subthreshold arbiter. The proposed PUF circuit is designed in TSMC 65 nm CMOS technology and verified by HSPICE tool. Experimental results show that the circuit can effectively resist model attacks and has an energy consumption of 0.23pJ/bit which is 20.67% lower than similar circuits.

       

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